Recently, a need is fell towards miniaturizing and enhancing the function and performance of electronic equipment, such that a technique for high density assembling of a semiconductor package has become indispensable. So far, a build-up substrate having a core layer has preferentially been used as an interposer substrate for a semiconductor package. However, the through-hole (TH) and the interconnect line width of a core substrate arc several times as long as the via diameter and the interconnect line width of the build-up layers. Such dimensional difference has so far been deterrent to increasing the operating speed and to realization of the high-density miniaturized interconnects. On the other hand, one of the sides of the build-up substrate is a layer unneeded as long as designing is concerned. However, it is provided to prevent the warping of the substrate, thus raising the cost. Hence, a coreless substrate, which is an all-layer build up substrate, not including a core layer, is sought to improve the operating speed and density as well as to reduce the cost.
On the other hand, in interconnecting a conventional interposer substrate (interconnect substrate) and a semiconductor element, a wire bonding, employing a gold wire or the like, or a flipchip method, employing a solder ball, has so far been used. However, both of these methods suffer from drawbacks. The wire bonding method is meritorious in reducing the cost. However, if the pitch is to be reduced, the wire diameter is to be decreased, thus possible leading to wire breakage or to a narrow connection condition. The flip-flop connection allows for high-speed signal transmission as compared to the wire bonding technique. However, in case the number of terminals of the semiconductor element is increased, or a connection pitch is narrowed, the connection strength of the solder bumps tends to be decreased, thus possibly producing cracking at the sites of connection or causing failures in connection due to voids. For this reason, a so-called semiconductor element enclosing substrate, in which a semiconductor element is enclosed in an interconnect substrate, and in which interconnects are directly led out at electrode terminals of the semiconductor element, has recently been proposed. This semiconductor element enclosing substrate has realized a high degree of integration and raised the functions of the semiconductor device. In addition, it has a number of advantages, including a thinner package, low cost, accommodation to high frequency and low-stress connection based on the plating technique.
In Patent Document 1, an IC chip is enclosed in a core substrate, and a transition layer is provided on a die pad of the IC chip, whereby electrical connection to the IC chip may be directly established without the interposition of a lead member.
In Patent Document 2, a multilevel substrate enclosing an electronic component is disclosed, in which the diameter of a transition layer 129 is set so as to be smaller than the diameter of a pad 127 and larger than an opening diameter 128a of a passivation film 128 that coats the pad, as shown in FIG. 19. By this arrangement, it is possible to prevent a crack in the passivation layer from an edge of the transition layer.
In Patent Document 3, which is not related with an interconnect substrate enclosing a semiconductor element, discloses providing a pad for connection to an electrical element and a terminal pad for connection to an external circuit on front and back sides of a multilevel interconnect substrate, as shown in FIG. 20. The diameter A of a via connecting to the electrical element is set so as to be smaller than the diameter B of a pad for connection to the external circuit.    [Patent Document 1] JP Patent Kokai Publication No. JP-P2001-339165A    [Patent Document 2] JP Patent Kokai Publication No. JP-P2004-288711A    [Patent Document 3] JP Patent Kokai Publication No. JP-P2005-72328A